Reference Guide

Logical levels

The simulator uses low, high and undefined logical levels. Actually undefined is not a certain level. It can be low or high. Undefined levels may appear at start time everywhere and when a tri-state output is floating.

Buffer truth table

In
Out
 0  0
 1  1
 u  u

Inverter truth table

In
Out
 0  1
 1  0
 u  u

Or gate truth table

In A
In B
Out
 0  0  0
 0  1  1
 1  0  1
 1  1  1
 0  u  u
 u  0  u
 u  u  u
 1  u  1
 u  1  1

Nor gate truth table

In A
In B
Out
 0  0  1
 0  1  0
 1  0  0
 1  1  0
 0  u  u
 u  0  u
 u  u  u
 1  u  0
 u  1  0

And gate truth table

In A
In B
Out
 0  0  0
 0  1  0
 1  0  0
 1  1  1
 0  u  0
 u  0  0
 u  u  u
 1  u  u
 u  1  u

Exor gate truth table

In A
In B
Out
 0  0  0
 0  1  1
 1  0  1
 1  1  0
 0  u  u
 u  0  u
 u  u  u
 1  u  u
 u  1  u

Exnor gate truth table

In A
In B
Out
 0  0  1
 0  1  0
 1  0  0
 1  1  1
 0  u  u
 u  0  u
 u  u  u
 1  u  u
 u  1  u

Nand gate truth table

In A
In B
Out
 0  0  1
 0  1  1
 1  0  1
 1  1  0
 0  u  1
 u  0  1
 u  u  u
 1  u  u
 u  1  u

Tri-state buffer truth table

In A
Enable
Out  Impedance
 0  0  u  high
 u  0  u
 high
 1  0  u  high
 0  1  0  low
 u  1  u  low
 1  1  1  low
 0  u  u  undefined
 u  u  u  undefined
 1  u  u
 undefined

In the case of high and undefined output impedance the undefined logical level implements some kind of worst case scenario.

Flip Flops

The set and clear inputs have priority. The undefined level on clock input may cause state change and undefined outputs. If the clock input of a positive-edge triggered flip flop changes (l->u or u->h) and other inputs (D or J,K) has been significantly changed since the previous sampling then the outputs will be undefined.


Flip Flop recovery time check

Flip Flop temoval time check

Flip Flop Tco

Flip Flop setup time check

Flip Flop hold time check



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